A conventional microprocessor die may operate in conjunction with one or more other integrated circuit dice, including but not limited to a chipset die or a Random Access Memory (RAM) die. In one common architecture, a microprocessor package including a microprocessor die is coupled to a memory controller hub (MCH) package including a chipset die that is in turn coupled to a bank of memory modules including one or more RAM dies. This architecture may be unsuitable for certain pin counts and/or signal speeds.
Recent systems have sought to address these and other limitations by including a microprocessor die and one or more other dice within a single package. FIG. 1 illustrates one such implementation, in which system 1 includes microprocessor die 2 and dynamic RAM (DRAM) 3 coupled to integrated circuit package substrate 4. System 1 may provide faster interface speed than the above-mentioned conventional systems. However, a size and a routing complexity of substrate 4 are greater than would be required to support die 2 alone.